The downlink scheduler is one of the key elements of a base station. Its main task is to assign radio resources to a pool of users. Radio resources may include spectrum, channel, coding and timing allocations for user communications.
Downlink scheduling is a sequential process that involves a sequence of steps. Downlink scheduling for Long Term Evolution (LTE) networks could for example comprise the following five steps: user weight calculation, user candidate selection, common control radio resource allocation, (e.g. physical downlink control channel (PDCCH) allocation in the case of LTE networks), multi-cell coordination and scheduling/link adaptation. These steps are performed in a scheduling interval, such as a transmission time interval (TTI).
A multi-core based processor is a processor to which two or more processor cores have been attached for enhanced performance, reduced power consumption, and more efficient simultaneous processing of multiple tasks. Due to the sequential nature of the downlink scheduling process and to the different requirements in terms of processing resources (e.g. digital signal processors (DSPs)), of each one of the steps, parallel operation on a downlink scheduler is not easily implemented to fully benefit from a multi-core architecture. Some processing resources (e.g. DSP cores) may be idle. In particular, for multiple users, the weight calculation step (or task) can be easily distributed in parallel to all available processing resources, as this step is performed on a per user basis (one processing resource can perform the step for one or more users, so all available resources can be used). However, subsequent steps in the process, such as candidate selection, PDCCH and scheduling/link adaptation are performed on a per cell basis. Thus, it is recognized herein, that if the number of cells is less than the number of available DSPs, there may be multiple idle DSPs during one scheduling interval. Furthermore, the multi-cell coordination step uses only one or a limited number of DSPs, possibly leaving the vast majority of DSPs idle. Also, signal timing variation is likely to create idle DSPs. For example, the PDCCH scheduling step will be delayed if a request signal from uplink required for the PDCCH scheduling step is late. It is recognized herein, that due to the sequential nature of the five downlink scheduling steps and the per cell use of processing resources by some steps, there will be a number of idle DSPs, indicating an inefficient use of processing resources, which can limit capacity, e.g., the number of users to which radio resources can be assigned at a time.